1. Field of the Invention
The present invention relates to a programmable logic cell array and, more particularly, to a programmable logic cell array architecture that efficiently supports demultiplexers and multiported register files.
2. Description of the Related Art
Programmable Logic Cell Arrays (PLCAs) are integrated circuits that contain configurable digital logic functions and routing resources. See e.g., Brandenburg et al., Poor Man's Gate Arrays: Logic Cell Arrays, IEEE Transactions on Nuclear Science, Vol. 35, No. 1, February 1988, pp. 213-216; Freeman, User-programmable Gate Arrays, IEEE Spectrum, December 1988, pp. 32-35. Through suitable programming, a PLCA can emulate a variety of different logic circuits. The ability to program and re-program PLCAs has proven to provide a great deal of flexibility to circuit designers.
The flexibility offered by PLCAs makes it possible to quickly prototype new logic designs without the expense of building the design from discrete components or fabricating the design in a custom integrated circuit. The trade-off, of course, is that since PLCAs are intended to support a wide variety of logic designs, the architecture of PLCAs must include routing and logic functionality that is unlikely to be used in all applications. Therefore, the efficiency or effective utilization of PLCA resources for a given application tends to be low compared to that which can be achieved in a custom integrated circuit implementation. This loss of efficiency is mitigated by the flexibility of the device, but there are some digital circuits which, when mapped onto a conventional PLCA, exhibit such extremely poor efficiency that implementing them in a PLCA (or a system of PLCAs) is impractical.
Because of their flexibility, PLCAs are important components in the construction of very high speed logic simulators or, more generally, configurable hardware systems (also called "virtual hardware"). See e.g., Kean et al., Implementation of Configurable Hardware using Wafer Scale Integration, 1990 International Conference on Wafer Scale Integration, pp. 68-73; Kean et al., Configurable Hardware: A new Paradigm for Computation, 1989 Decennial Caltech Conference on VLSI. In such applications, hundreds or thousands of PLCAs are connected electrically to form a prototype testbed for designing and experimenting with new digital system designs. A new design is "mapped" onto the simulator by programming the component PLCAs so that the simulator as a whole functionally emulates the behavior of the system being designed. This makes it possible to design, debug and test large, complex logic systems (such as computer processors, graphics engines, digital signal processing systems, etc.) much faster than is possible using conventional tools, such as software simulation and hardware prototyping.
An important component of many new high speed digital circuit designs (e.g., computer processor designs) is a multiported register file (an array of registers that can be read and written on many different ports simultaneously). Hence, in order for a logic simulator constructed from PLCAs to support the development of such digital circuit designs, it is desirable to map such register files onto PLCAs. Unfortunately, a serious problem exists which makes it impossible to map demultiplexers or register files into known PLCA architectures with sufficient efficiency to be practical.
When multi-ported register files are implemented with pure Boolean logic, they require a large number of gates. For example, an 80-bit wide file of 96 registers with four write ports and eight read ports requires more than 250,000 2-input gates or logic functions. It is estimated that such a multiported register file would require over 400 conventional PLCAs to be represented, if it can be done at all.
One might hope that expressing such a circuit in terms of 6-input, 2-output logic cells might lead to a significant reduction in the number of logic functions needed, since this has been observed to occur for many other circuits. For example, Xilinx Corporation of San Jose, Calif. has PLCA software that can take a circuit consisting of 2-input, 1-output gates and transform it to a logically equivalent circuit of 5-input, 2-output gates (logic functions), often achieving a reduction in the number of needed gates by a factor of 10 or more. However, this does not happen for demultiplexers (decoders) or multi-ported register files. For example, the register file mentioned above compresses to approximately 90,000 6-input, 2-output gates (logic functions), which is a very low amount of compression compared to many other circuits. Using PLCAs containing 256 6-input, 2-output logic cells (which is a fairly typical number of existing PLCAs) to implement the register file, would require a minimum of 350 of them, assuming infinite routing resources and no I/O pin limitations. Many more PLCAs that this are likely to be required in practice.
Another approach might be to handle a multi-ported register file as a special case by building it out of discrete components and interfacing it to the simulator. However, this approach is not practical for a number of reasons. One reason is that the special case approach requires a large number of discrete, off the shelf components (e.g., more than 100). Another reason is that the special case approach requires a large number of signals to be interfaced to the simulator (e.g., more than 1000). Yet another reason why the special case approach is impractical is because it is inflexible with respect to the register file parameters (e.g., bit width, number of registers, number of ports).
Thus, there is a need for a PLCA architecture that can efficiently support demultiplexers and multiported register files without sacrificing PLCA functionality or flexibility.